A chip design process has a plurality of discrete phases that include but are not limited to conception, architecture design, register-transfer level (RTL) design, physical design, and tape-out. Some of the key metrics to measure success of a chip design project are timeliness, correctness and completeness of the design. One way to enhance timeliness and to reduce time-to-market of the chip design project is to achieve the objectives of completeness and correctness as early in the design process as possible. Since RTL design verification is typically the most time-consuming phase in the chip design process, an approach to accelerate RTL verification will reduce the overall project time.
In practice, multiple chip design projects may overlap in time and different groups in a chip design team may work on different design phases of these projects at the same time. For example, when the RTL design group is taping out one of the projects, the chip design architects may be working on another project. Similarly, when the RTL design group is in the RTL design phase of a project, the verification group may be incorporating new features into the chip verification environment. As such, there is an opportunity for parallelism and pipelining among of the chip design projects that will increase the throughput of the chip design team by automating the transfer and sharing of knowledge among the different groups in the team.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent upon a reading of the specification and a study of the drawings.